0195136047.pdf

6.2 DIGITAL SYSTEM COMPONENTS 299

S 1

S 1 S 0

I 1 S^0

I 0

I 0

I 1

I 2

I 3

I 2

I 3

0

Select Lines

Select Lines

Input

lines

Output

Output 0

01

10

11

Q

Q

I 0

I 1

I 2

I 3

S 1 S 0

Q

(b)

(c)

(a)

Figure 6.2.34-to-1 multiplexer.(a)Block diagram.(b)Truth table.(c)Logic diagram.

simultaneously. However, the output of each flip-flop drives only an adjacent flip-flop. A single
pulse propagates through the ring in a ring counter, whereas all remaining flip-flops are at the
zero state.
Figure 6.2.5(a) shows a block diagram of a 3-bit ripple counter using JKFFs. Notice from the
timing diagram shown in Figure 6.2.5(b) that the outputQ 0 of the leftmost flip-flop will change
its state at every clock pulse if the clear signal equals zero. The outputQ 1 , controlled byQ 0 ,
will change its state every timeQ 0 changes from 0 to 1. SimilarlyQ 2 is controlled byQ 1. Figure
6.2.5(c) shows the outputs for the first 8 clock pulses. Observe that a 3-bit counter will cycle
through 8 states, 000 through 111. Ann-bit ripple counter, in general, will cycle through 2nstates;
it is known as adivide-by-2ncounterormodulo-2nbinary counter.Taking the outputs fromQ 2 Q 1
Q 0 , the counter becomes anup-counter;taking the outputs fromQ ̄ 2 Q ̄ 1 Q ̄ 0 , the counter becomes
adown-counter,which counts down from a preset number. Asynchronous ripple counters are
available as MSI packages.