0195136047.pdf

300 DIGITAL BUILDING BLOCKS AND COMPUTER SYSTEMS

D 3

Ck

Clock

Data input

Preset

Data output

Clear

(a)

(b)

FF3

Pr

Clr

Y 3 D 2

Ck

FF2

Pr

Clr

Y 2 D 1

Ck

FF1

Pr

Clr

Y 1 D 0

Ck

FF0

Pr

Clr

Y 0

Y 3

Y 2

Y 1

Y 0

Pulse 1

Clock

Data

input

2

T 2 T 3 T 4 T 5 T

T 2 T 4 T 5 T

6 T

3 T 4 T 6 T

4 T 5 T

2 T 3 T 5 T 6 T

5 T 6 T

3456

Figure 6.2.44-bit shift-right SISO register.(a)Block diagram.(b)Timing diagram.

J 0

k 0

Clear

Clock

Logic 1

(a)

Ck 0

Clr

Q 0

Q 0

J 1

k 1

Ck 1

Clr

Q 1

Q 1

J 2

k 2

Ck 2

Clr

Q 2

Q 2

Figure 6.2.53-bit ripple

counter.(a)Block diagram.

(b)Timing diagram.(c)Out-

puts for the first 8 clock

pulses.