8.2 BIASING THE FET 395
RC=
3 VCC
8 ICQ
(8.1.1)
RE=
VCC
8 (ICQ+IBQ)
=
VCCβ
8 ( 1 +β)ICQ
(8.1.2)
Noting thatVB=VE+VBEin Figure 8.1.1, orVB=(VCC/ 8 )+ 0 .7 for silicon, and selecting
I 2 = 5 IBQ, it follows then
R 2 ∼=
0. 7 +(VCC/ 8 )
5 IBQ
(8.1.3)
R 1 ∼=
VCC−VB
6 IBQ
=
( 7 VCC/ 8 )− 0. 7
6 IBQ
(8.1.4)
EXAMPLE 8.1.1
Apply the rule-of-thumb dc design presented in this section for a siliconnpnBJT withβ= 70
when the operatingQpoint is defined byICQ=15 mA andIBQ= 0 .3 mA, with a dc supply
voltageVCC=12 V, and find the resistor values ofRC,RE,R 1 , andR 2.
Solution
Applying Equations (8.1.1) through (8.1.4), we get
RC=
3 ( 12 )
8 ( 15 × 10 −^3 )
= 300
RE=
12 ( 70 )
8 ( 71 )( 15 × 10 −^3 )
= 98. 6
R 1 ∼=
[7( 12 )/8]− 0. 7
6 ( 0. 3 × 10 −^3 )
= 5444
R 2 ∼=
0. 7 +( 12 / 8 )
5 ( 0. 3 × 10 −^3 )
= 1467
8.2 Biasing the FET
Let us first consider biasing the JFET and then go on to biasing the MOSFET.
Biasing JFET
A practical method of biasing a JFET is shown in Figure 8.2.1. Neglecting the gate current, which
is usually very small for a JFET, we have
VG=
VDDR 2
R 1 +R 2
(8.2.1)
The transfer characteristic of the JFET [see Figure 7.4.3(c)], neglecting the effect ofvDSoniD,is
given by
iD=IDSS
(
1 +
vGS
VP
) 2
(8.2.2)
