0195136047.pdf

8.2 BIASING THE FET 397

or

RD=

VDD−IDQRS−VP

2 IDQ

=

3 (VDD− 2. 923 VP)

2 IDSS

(8.2.12)

Note that the source voltageVDDmust be larger than the minimum necessary to maintain adequate
voltage swings for ac signals. A value of 4.923VPis considered to be a reasonable minimum in
order to allow peak collector voltage changes of±VP.

EXAMPLE 8.2.1

Consider and obtain the values forRS,R 2 ,R 1 , andRD. Apply the rule-of-thumb dc design
procedure outlined in this section for a JFET withVP =3V,IDSS =20 mA, and a source
voltageVDD=24 V.

Solution

Applying Equations (8.2.8) through (8.2.10),

RS=

5. 768 VP

IDSS

=

5. 768 ( 3 )

20 × 10 −^3

= 865. 2 

R 2 = 100 RS= 86 , 520 

R 1 = 100 RS

(

VDD

1. 5 VP

− 1

)

=86,520

(

24

1. 5 × 3

− 1

)

=374,920

From Equation (8.2.12),

RD=

3 (VDD− 2. 923 VP)

2 IDSS

=

3[24− 2. 923 ( 3 )]

2 × 20 × 10 −^3

= 1142. 3 

Note thatVDD=24 V is greater than 4. 923 VP = 14 .77 V; the device is biased above the
reasonable minimum.

The dc design procedure may have to be adjusted after the ac design in some cases because
of signal values, and refined further to suit the available components and power-supply voltages.
In any case, one should ensure that any transistor maximum rating is not exceeded.

Biasing Depletion MOSFETs

Recognizing thatvGScan exceed zero in a MOSFET and hence the operating point may be placed
at a higherIDQthan in a JFET circuit, the same procedure as that outlined for dc biasing of JFETs
can be applied directly to the biasing of depletion-type MOSFETs.

Biasing Enhancement MOSFETs

A biasing method for ann-channel enhancement-type MOSFET is illustrated in Figure 8.2.2.
Since the gate draws no current,VGis given by

VG=

VDDR 2

R 1 +R 2

(8.2.13)

Note thatRSin Figure 8.2.2 is only to provide operating-point stability and not to establish a
quiescent point since its voltage drop is not of the correct polarity. Neglecting the effect ofvDSon
iD, the drain current for the active mode is given by [see Equations (7.4.2) and (7.4.3)]