9.3 CMOS AND OTHER LOGIC FAMILIES 433FET switches offer significant advantages over BJT switches. An FET switch does not draw
current from a previous stage because the gate current of an FET is practically zero. Consequently,
no significant power-loading effects are present, whereas BJTs, in contrast, do load down previous
stages. Another advantage of FETs is that their logic voltage levels (typically,VDD=15 V) are
higher than those of the BJTs (typically,VCC=5 V). Thus, the FET logic circuits tend to tolerate
more noise than the comparable BJT logic circuits. However, their switching speeds tend to be
somewhat smaller than those for BJTs in view of the larger inherent capacitances of the FETs.
MOSFETs are preferred over JFETs for digital integrated circuits. Either PMOS (p-channel
metal-oxide semiconductor) or NMOS (n-channel metal-oxide semiconductor) logic circuits can
be constructed. Requiring only about 15% of the chip area of a BJT, MOSFETs offer very high
packing densities.
The usage of ap-channel MOSFET as the active load for ann-channel MOSFET leads
to a logic family known as complementary-symmetry MOS, or CMOS. CMOS technology has
significant advantages and has become most popular. A basic CMOS inverter is shown in Figure
9.3.2(a), in which both ap-channel and ann-channel enhancement MOSFET are used as a
symmetrical pair, with each acting as load for the other.
When the inputvinis low, the gate–source voltage of the NMOS is less than the threshold
voltage and is cut off. The gate–source voltage of the PMOS, on the other hand, is−VSS, where
VSS, the supply voltage, is greater than the threshold voltage,VT. Then the PMOS is on, and the
supply voltage appears at the outputvout. When the inputvinis high (vin∼=VSS), the PMOS turns
off; the NMOS turns on. ThenVSSappears across the drain–source terminals of the PMOS and
the outputvoutdrops to zero. Thus, the circuit functions as an inverter. Figure 9.3.2(b) shows the
simplified circuit model of the CMOS inverter by depicting each transistor as either a short or an
open circuit, depending on its state.
Note that when the output is in the high state, the PMOS is on with the NMOS being off;
when the output is in the low state, the NMOS is on with the PMOS being off. Virtually no current
is drawn from the power supply in either case. The CMOS has the advantage that it uses no power
except when it is actually switching. This property of virtually no power consumption, coupled
with the small chip surface needed, makes the CMOS very favorable for miniature and low-
power applications such as wristwatches and calculators. Because of the poor switching speeds
(compared to TTL), they are applied to low- to medium-speed devices. The principal disadvantage
of the CMOS is a more complex fabrication procedure than that of the NMOS, leading to more
defects and higher cost.
Figure 9.3.2CMOS inverter and circuit model.