siliconchip.com.au Australia’s electronics magazine May 2019 33
differential filtering, to keep out any signals at 6.144MHz
or above (the ADC’s internal clock rate), which could affect
the signal quality through aliasing.
Analog to digital conversion
The stereo differential signals are applied to input pins 16,
17, 20 & 21 of IC1. There are some extra components con-
nected to this IC, which are required for its correct operation.
It has two internal reference voltages, which are fed to
pins 22 (VQ or quiescent voltage) and 24 (FILT+) and these
need to be externally bypassed to ground via capacitors. We
have provided two capacitors to filter each of these rails,
10nF in both cases, plus 220μF for FILT+ and 1μF for VQ.
The use of two different values provides a lower imped-
ance across a broader range of frequencies.
IC1 has three different supply pins: VA (pin 19) for the
analog 5V supply, VD (pin 6) for the digital 5V supply and
VL (pin 8) for the 3.3V logic/interface supply. The supply
arrangement is described below.
Pin 1 is IC1’s reset input, and this is connected to the
logic supply via a diode and resistor, and to ground via a
capacitor. This forms a power-on reset circuit. Initially, the
capacitor is discharged and so the reset input is low, reset-
ting IC1. This capacitor then charges up via the 10kresistor
and releases reset after a few milliseconds. When power
is switched off, the capacitor rapidly discharges via D13.
This reset pin is also connected to pin 2 of CON2, which
is routed to the microcontroller, so it can reset IC1 after
power-up if necessary.
Pin 2 selects either master mode (when high, ie, IC1
drives the digital audio clock lines) or slave mode (when
low, ie, IC1 is clocked externally). This is connected directly
to ground since the audio clock signals are supplied from
the microcontroller via pins 12, 14 and 16 of CON2. These
connect to pins 5, 3 and 4 of IC1 respectively, and in slave
mode, these are the clock inputs.