34 Silicon chip Australia’s electronics magazine siliconchip.com.au
Pin 5 (MCLK) is the master (oversampling) clock, which
is typically around 12.288MHz, ie, 48kHz x 256. This is
used to clock the ADC modulator and other internal cir-
cuitry. Pin 3 is the left/right clock or sample clock, and this
is usually at around 48kHz. When it is high, the serial data
pin is normally carrying left audio channel data when it is
low, right audio channel data.
Pin 4 is the sample clock and this clocks the serial data
itself. It usually operates at the sampling rate times the
number of channels, eg, 48kHz x 2 = 96kHz. The serial data
comes from pin 9 of IC1 and goes to pin 18 of CON2, where
it eventually feeds into the microcontroller.
Note that pin 5 (MCLK) of IC1 has a snubber network con-
nected to ground. This is intended to prevent ringing and
is a good idea when a high-frequency signal is fed through
a long wire, however, at 12.288MHz it was found not to be
necessary, and so those components can be safely left off.
ADC configuration
Pins 10-14 of IC1 are configuration inputs and their state
determines how the ADC operates.
Pin 10 (MDIV) causes the master clock signal to be divid-
ed by two when high, allowing a higher frequency master
clock to be used. Pin 11 enables or disables a digital high-
pass filter, to remove any DC offset from the input signals.
Pin 12 selects the digital audio output data format, either
I^2 S or left-justified.
Pins 13 & 14 select the sampling rate range, either single-
speed mode (2-51kHz, M0 & M1 low), double-speed mode
(50-102kHz, M0 high) or quad-speed mode (100-204kHz,
M1 high).
Of these five pins, pin 12 (I2S/LJ) is tied to VL via a
10kresistor, permanently selecting I^2 S format. The other
four connect to jumpers JP1-JP4 and have 10kpull-ups to
VL. So they are high by default but can be pulled low by
placing a shorting block on the jumper.
Typically, all four jumpers are fitted, so that master clock
division is disabled, the high-pass filter is enabled and the
sampling rate can be 48kHz.
But the use of jumpers means that you could change the
software (eg, to use a higher sampling rate) and easily re-
configure the ADC board to suit.
Pin 15 of IC1 goes low if either input signal swings out-
side the range that the ADC can cope with. We have an LED
(LED1) connected to this pin, with a 1kcurrent-limiting
resistor to VL. So LED1 will light if the input signal level is
too high for IC1 to cope with, resulting in digital clipping.Power supply rails
The 5V analog supply comes from the output of an
MC33375D low-dropout regulator, REG1, which is fed from
the incoming +9V supply via a ferrite bead (FB3). This regu-
lator was chosen for its very tight line and load output spec-
ifications (2mV and 5mV respectively), which means that
the resulting analog 5V rail should be very stable indeed.
REG1 has 100nF and 220μF input bypass and output fil-
ter capacitors, but there are also four bypass capacitors right
near IC1’s VA input pin: 10nF, 100nF, 1μF and 10μF. Again,
these different values were paralleled to provide a very low
supply source impedance for IC1 across a wide range of fre-
quencies, from a few hertz up to many megahertz.
The 5V digital supply, VD, is powered from the same 5V
rail as VA but with a 5.1resistor in between so that digi-
tal noise does not feed back into the analog supply. The
VD rail has a separate 10nF bypass capacitors for high-fre-
quency stability.
The 3.3V logic supply comes from pin 20 of interface
header CON2, via another ferrite bead (FB6) and is bypassed
with 10nF, 100nF and 1μF capacitors.
The ±9V supply rails for the op amps (also used to derive
the 5V rails) are fed in via pins 24 & 26 of box header CON2,
with series ferrite beads to stop RF signals from propagating
in either direction. This is important since long unshielded
ribbon cables can pick up all sorts of EMI.Microcontroller interface
CON2 carries the power supply, control and digital audio
signals. It’s a 26-pin DIL header which connects to a ribbon
cable. By tying all odd numbered pins to ground (except for
pin 25), every second wire in the ribbon cable is grounded,
minimising interference between adjacent signals on the
even-numbered pins.
As previously mentioned, pins 20, 24 & 26 provide power
to the ADC board while pins 12, 14, 16 & 18 carry the clock
signals and digital audio data, and pin 2 is the reset line.
Pins 22 & 25 are unused, leaving pins 4, 6, 8 & 10 which are
reserved for an SPI control bus.
But IC1 does not have an SPI control interface, so those
pins are not routed anywhere on this board.DAC circuitry
Now let’s turn our attention to the DAC board circuit,
shown in Fig.5. Essentially, its job is the opposite of the
ADC circuit shown in Fig.4.
Rather than turning two analog audio signals into digital
data, this circuit takes digital data and produces two low-
distortion analog audio signals.
DIL header CON3 is another 26-pin header and it uses es-
sentially the same pinout as CON2 in Fig.4. As before, odd
numbered pins other than pin 25 are tied to ground. Pins
20, 22, 24 & 26 supply power to the DAC module while pin
2 is reset, pins 4, 6, 8 & 10 are the SPI control bus and pins
12, 14, 16 & 18 carry the digital audio clocks and data.
As with the ADC board, there is a snubber on the MCLK
line (at pin 6 of IC6), but this is not strictly necessary and
can be omitted. Also, there is no automatic reset networkKeep your collection of your
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