FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

u

use IEEE.numeric_std.ALL;

entity counter is
Generic(number_of_bits: integer := 8);
Port ( clk : in STD_LOGIC;
ce : in STD_LOGIC;
r : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (number_of_bits - 1 downto 0));
end counter;

architecture Behavioral of counter is

constant all_zeros: std_logic_vector(number_of_bits - 1 downto 0) := (others => '0');

signal q_buf: std_logic_vector(number_of_bits - 1 downto 0) := (others => '0') ;

begin

q <= q_buf;

process(clk)

begin

if rising_edge(clk) then

if r = '1' then

q_buf <= all_zeros;

elsif ce = '1' then

q_buf <= q_buf + '1';

end if;

end if;

end process;

end Behavioral;

testB_counter.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.ALL;

entity testB_counter is
end testB_counter;

architecture Behavioral of testB_counter is
component counter is
Generic(number_of_bits: integer := 8);