FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

v

Port ( clk : in STD_LOGIC;

ce : in STD_LOGIC;

r : in STD_LOGIC;

q : out STD_LOGIC_VECTOR (number_of_bits - 1 downto 0));

end component;

signal clk: std_logic := '0';

signal ce : std_logic := '1';

signal r : std_logic := '0';

signal q : std_logic_vector(7 downto 0) := (others => '0');

signal cnt: std_logic_vector(7 downto 0) := (others => '0');
begin

clk_gen: process

begin

clk <= not clk;

wait for 5 ns;

end process;

process(clk)

begin

if rising_edge(clk) then

cnt <= cnt + '1';

if cnt = x"0f" then

cnt <= x"00";

end if;

end if;

end process;

process(clk)

begin

if rising_edge(clk) then

if cnt = x"00" or cnt = x"03" or cnt = x"06" or cnt = x"09" then

ce <= not ce;

end if;

if cnt = x"01" or cnt = x"0c" then

r <= '1';

else

r <= '0';

end if;

end if;