lektor January & February 2021 23The serial clock (SCK or SCLK) must be
12.288 MHz (2 channels * 192 kHz * 32 bit).
Since the maximum clock frequency of the
microcontroller is 20 MHz, the only way to
output serial data (SD or SDATA) faster is
to use an external parallel-in serial-out shift
register and use the clock of the microcon-
troller to clock the shift register. PB0 must
be configured as CLKO (Clock Out) when
programming the fuses of the ATmega328.
The complete schematics of the signal gener-
ator can be seen in Figure 1. Apart from the
shift register a ripple counter, a flipflop and
some Exclusive-ORs are added to free the
microcontroller from other (timing) tasks than
just outputting the bytes of the samples.It would be obvious to use a microcontroller
that supports I2S for this task, but why not
use a very common microcontroller like the
ATmega328P instead? The problem of course
is that it doesn’t support I2S. It was quite a
challenge to build a digital sine wave genera-
tor with I2S output using this microcontroller
and some additional hardware, but this project
shows that it can be done! The firmware of
the ATmega is developed in BASCOM-AVR.Some extra hardware is needed
The goal is to create an I2S signal with 32-bit
data at a sample rate of 192 kHz, which is
close to the maximum sample frequency of
the PCM1794A used in our RPi audio DAC.Since its introduction in 1986, the Inter-
Integrated Circuit Sound (I2S) bus has been
the “de facto” standard for transmission of serial
digital audio signals. During the development
and test of our “Audio DAC for the Raspberry
Pi” [1], we came up with the idea to design a
dedicated circuit that generates an I2S signal
to test the DAC without connecting the RPi as
signal source. This circuit can of course also be
used to test other audio DACs with I2S inputs,
provided that they can handle the 192 kHz
sampling frequency and 24- or 32-bit audio data.
Design options
To build an I2S test signal generator, one
option would be to use a 24-bit ADC with
I2S outputs, with a signal (sine wave) genera-
tor as input. But to check if the analog output
signals of the DAC are indeed flawless, the
sine wave in the I2S signal must be perfect
to perform proper distortion measurements.
The test signal should not be degraded by
an inferior analog source or ADC in any way.
As an alternative, a microcontroller can be
used to generate the I2S signal, using a table
with 32-bit samples that can be accurately
calculated to ensure the quality of the audio
data. This will generate a signal that is perfect
for distortion measurements, in this case a
1 kHz sine wave with 192 kHz sample rate.
(^11) RESET
Q12^1
Q11^15
Q10^14
Q9^12
Q8^13
Q7^4
Q6^2
Q5^3
Q4^5
Q3^6
Q2^7
Q1^9
(^10) CLK
74 AC4040
16
8
VCC
14
7
VCC
R4
150R
C4
22p
CLK
CLK
X1
12.288MHz
C122p C222p
VCC 1
2 =1^3
IC4A
4
(^6) = 1 5
IC4B
9
10 =1^8
IC4C
12
13 =1^11
IC4D
(^2) D
(^3) CLK
S
4
R
1
Q^5
Q^6
IC5A
(^12) D
(^11) CLK
S
10
R
13
Q^9
Q^8
IC5B
14
7
VCC
C5
100n
C6
100n
C7
100n
C8
100n
C9
100n
VCC 192kHz
12.288MHz
32bit
IC2IC3IC4IC5
2 1
4 3
6 5
K1
R3
10k
VCC
C3
100n
(^1) PC6/RESET
PD0^2
PD1^3
PD2^4
PD3^5
PD4^6
VC C
7
8 GNDPB 7 9 PB 6
10
PD5^11
PD6^12
PD7^13
(^14) PB0/CLKO
(^15) PB1
(^16) PB2
(^17) PB3/MOSI
(^18) PB4/MISO
(^19) PB5/SCK
AVC C
20
AREF
21
GND
22
(^23) PC0
(^24) PC1
(^25) PC2
(^26) PC3
(^27) PC4
(^28) PC5
IC1
ATmega328P-20PU
ISP
K2
SDATA
SCLK
LRCLK
SDATA
SCLK
LRCLK
K3
3V3..5V
R1
2k2
LED1
(^12)
(^34)
65
A 987
CB
DE
F (^012)
4
8
C
S1
I2S
S2
R2
100R
Reset
IC5=74HC74
(^10) SER
(^11) A
(^12) B
(^13) C
(^14) D
(^3) E
(^4) F
(^5) G
(^6) H
(^2) CLK
(^15) INH
(^1) SH/ LD
QH^9
QH^7
74HC165
16
8
VCC
IC4=74HC86
LR
SC
SD
IC2
IC3
HC4040 CLOCK
Q1
Q2
Q3
Q4
Q5
2nd byte 3rd byte 4th byte (LS) 1st byte (MS)
Q6
1st byte (MS)
CLK=SCLK=12.288 MHz, fs = 192kHz
LRCLK (fs)
with exor's from Q4
HC165 QH bits
HC165 LOAD
3130292827262524232221201918171615141312111098765 43210
I2S: SDATA is clocked on the low to high transition of SCLK
HC165 CLOCK
bit 31 = MSB
bit 0 = LSB
3 zero-bytes + extra NOPs before Do-Loop to start MSB-byte at correct moment
74HC74 SDATA 313029282726252423222120191817161514131211109876 54321031302928272625
3130292827262524
window port D7 clock cycles
HC4040 RESET
Figure 1: Schematic of the I2S signal generator.
Figure 2: Timing diagram.
PROJECT DECODER
Ta g s
Digital audio, Raspberry Pi, DAC, I^2 S
Level
entry level – intermediate level – expert level
Time
About 4 hours
To o l s
Soldering tools (through-hole), AVRISP
Cost
Approx. €15