24 January & February 2021 http://www.elektormagazine.com
A 74AC4040 (IC3, 12-stage binary ripple
counter) is used to properly align the I2S
signals. This counter advances on the falling
edge of the clock input. It also has a master
reset (pin 11) that can be used to synchronize
it with the microcontroller. The sixth flip-flop
(pin 2) divides 12.288 MHz by 64 and outputs
exactly 192 kHz, the frequency we need for
the word select line.At the start of the program, the reset of the
counter is activated (high). It is deactivated
just before the start of the main loop (i.e.,
about a quarter of a second after power up,
which is all the time it takes to create the
array). This reset signal synchronizes the data
at the output of the shift register and the word
select line. First three samples with value 0
and a few NOPs are used so the first byte is
at the output of SDATA at the correct moment.
There is a window of seven clock cycles for
the first MS-byte to be clocked into the shift
register. Each byte at port D is replaced by the
next after eight clock cycles. In other words,
the moment the first MS-byte at port D can
change relative to the load pulse of the shift
register may vary seven clock cycles (see
timing diagram). The data at the output of
port D changes a few nanoseconds after the
rising edge of CLKO (PB0).An 8-bit parallel-in/serial-out shift regis-
ter 74HC165 (IC2) is used for serial data. It
has an active low parallel load (pin 1) and
a clock (pin 2) with inhibit (pin 15, active
low enable) which have the same function-
ality (both internally connected to an OR
gate). Depending on component place-
ment swapping connections can simplify
routing. Data is shifted on the rising edge of
the clock. The serial input (pin 10) is not used
and connected to ground. The load pulse (LD,
active low) for the shift register is derived
from counter output Q4 using Quad 2-Input
Exclusive-OR 74HC86 (IC4). The signal to pin
4 of IC4B is inverted and delayed by IC4A
by its propagation delay and an extra delay
of a few nanoseconds by R4/C4. Because
of the Exclusive-OR function each change
of Q4 gives a short active low pulse at the
output of IC4B. The pulse is long enough to
load the new data into the shift register but
short enough to be inactive before the rising
edge of the clock. To load the data from port
D into the shift register at the correct moment
the pulse must be active just after the rising
edge of the clock (pin 1). This means the
clock of the shift register must be inverted,
which is done by IC4C.The hardware, in more detail
The timing diagram in Figure 2 can help to
choose the external components. The I2S
bus comprises three signals: the serial data
(SDATA) is clocked on the rising (low-to-high)
edge of the serial clock (SCLK) and the word
select line (WS or LRCLK) indicates the audio
channel (0 for left, 1 for right). Its frequency is
equal to the sampling frequency of the digital
audio signal (192 kHz) and can be derived
from the serial clock. The serial data and word
select line both must change on the falling
(HIGH-to-LOW) edge of the serial clock. The
HC-logic family is in principle fast enough to
be used as external components, although
propagation delay of the gates must be
corrected at one point: 12 ns delay is almost
15% of the microcontroller’s clock period. All other software tasks, like calculating the
32-bit sine wave and creating the array of
sample bytes, must be done before the main
loop of the program starts. The 32-bit samples
are divided into four bytes. This means the
size of the array must be 4 * 192 = 368 bytes.
Left and right channel use the same signal, so
each group of four bytes per sample must be
repeated. The number of lines this part of the
main loop takes can be calculated:
2 channels 4 bytes 192 samples * 4 lines
– 3 = 6141 program lines
After the last sample byte in the loop, the three
NOPs are omitted as the restart of the loop
takes three clock cycles, which explains the
“-3” in this calculation.
COMPONENT LIST
Resistors
R1 = 2.2 k
R2 = 100 Ω
R3 = 10 k
R4 = 150 ΩCapacitors
C1,C2,C4 = 22 pF, C0G/NP0,
lead spacing 5 mm
C3,C5,C6,C7,C8,C9 = 100 nF, X7R,
lead spacing 5 mmSemiconductors
LED1 = LED, green, 3 mm
IC1 = ATmega328P-PU, 20 MHz, DIP28
IC2 = 74HC165
IC3 = 74AC4040 – do not use HC logic !!!IC4 = 74HC86
IC5 = 74HC74Other
K1 = 2x3 pin header, vertical, pitch 2.54 mm
K2 = 1x4 pin header, vertical, pitch 2.54 mm
K3 = Terminal block 5.08 mm, 2-way, 630 V
S1 = Rotary Coded Switch, hexadecimal, real
code, THT (e.g. Nidec Copal Electronics
SD-1010)
S2 = Switch, tactile, 24 V, 50 mA, 6x6 mm
X1 = Crystal 12.288 MHz, C-load 18 pF, 10 ppm,
HC-49S
PCB 200253-1 v1.1Figure 3: PCB layout.