of all data requests. Therefore, replacing your memory with new memory that is 100 per-
cent faster would gain you about a 5 to 10 percent gain in performance.
If you increase the size of your RAM with a faster memory, remember that the speed
of the memory in Bank 0 is the speed the BIOS will set as your memory speed. There are
also dangers associated with mixing memory of different speeds. See Chapter 7 for more
information.Tag RAM
As previously discussed, cache memory can be internal or external, level 1 or level 2.
In addition, level 2 cache is divided into two parts: Data store The area of L2 cache where the data being cached is stored.
The data store’s size (256K is very common) sets the capacity of the cache.
Tag RAM The number of bits of tag RAM (eight bits is typical) directly
determines how much of primary memory can be cached and if a cache
search will result in a hit or a miss.A PC with 256K of data store in its L2 cache and eight bits of tag RAM is capable of
caching 64MB of RAM. In order for your PC to cache more primary memory, the number
of bits of tag RAM must be increased. The amount of data store on a PC does not deter-
mine how much RAM is cached, as is commonly assumed. It is the number of tag RAM
bits that controls the caching capacity. Tag RAM is included in the chipset of most sys-
tems (see Chapter 5 for more information on chipsets), and upgrading a PC’s chipset is
one way to increase the number of tag RAM bits. The chipsets on some PCs, such as the
Pentium Pro, are configured to support caching of up to 4GB of RAM. Some mother-
boards include an expansion socket for a tag RAM chip to be installed to add additional
bits. Check the documentation of your PC’s motherboard to determine its tag RAM size
andwhetheritcanbeupgraded.AddingmoredatastorewithoutthetagRAMtosupport
it is a waste of your time and money.Moving Data in and out of the Cache
The data store (L2 cache) is organized into a series ofcache lines, which are 32-byte blocks
of data. Data is moved in and out of the data store 32 bytes (256 bits) at a time. Since the
width of the data bus of most newer PCs is 64 bits, moving data to or from the CPU re-
quires the cache line to be broken up into four 64-bit blocks and transmitted separately.
The sum of the data sent in the four blocks is called aburst. When data is requested
from cache by the CPU, assuming the data is in cache, the first 64 bits of data take longer
to send since they must locate the data in cache and send it out over the bus. Once the
location of the remaining three blocks of 64 bits each is known, no time is lost looking for
them and they are each sent along their way. For example, if the first 64-bit block takes
four clock cycles, and each of the other three blocks takes one clock cycle, the timing for
the burst is 4-1-1-1. This notation, which shows the number of clock cycles required to
address, look up, and send each block in the burst, is the burst timing of the cache. Most(^162) PC Hardware: A Beginner’s Guide