cache systems include a burst timing in their specifications. None of the numbers in the
burst timing are as important than their total value, which in this case is seven, meaning it
takes seven clock cycles to complete the delivery of the requested data.The Impact of a Cache Miss
As indicated in the previous section, there is a delay involved while the cache checks to
see if the data requested is in the data store. If the data is not in cache (a cache miss), clock
cycles are used looking for it. At this point, the data is requested from RAM. The impact
of this is that the clock cycles used looking for the data in cache must be added to the time
required to find and transfer the data from main memory. If 10 total clock cycles are
normally required to transfer a data burst from RAM and a cache miss takes 2 clock
cycles,eachcachemissresultsin12clockcyclesbeingrequiredtogettherequesteddata
to the CPU. So a cache miss has a direct impact on the PC’s performance.
A PC with not enough L2 cache can result in too many cache misses. A small data
store translates into a low cache hit ratio and too much data served from RAM. If the PC is
capable of supporting it, increasing the size of the external cache also increases the
chances of cache hits, which also means it decreases the chances of a cache miss. The size
of the data store has no impact on the time used to see if requested data is in cache. There-
fore, adding more L2 cache increases the chance of finding the data in cache without an
increase in the overhead used to find it.Cache Memory Types
Functionally, there are three types of cache memory used on PC systems: asynchronous,
synchronous, and pipelined burst. Their primary differences are in their timing and the
level of support they require from the PC’s chipset. In fact, the chipset and motherboard
have the most to do with which type of cache memory is used on a PC. Asynchronous cache Asynchronousmeans that data is transferred without
regard to the system clock’s cycles. This type of cache memory is the slowest of
the three, primarily because it transfers data without using system clock cycles.
Asynchronous cache is common on 486 PCs, but because it requires nearly
twice the cycles to transfer data at speeds of 66MHz or higher, it wasn’t used
on systems with speeds higher than 33MHz.
Synchronous cache Synchronous cache, also known assynchronous burst
cache, ties its activities to the system clock’s cycles. In order to avoid problems
such as system crashes or lockups, the speed of the SRAM used to implement
this cache must match the system’s bus speeds. However, like asynchronous
cache, synchronous cache has problems at higher bus speeds and is being
replaced by pipeline burst cache.
Pipelined burst This improvement on synchronous cache memory transfers
usespipeliningtechnology to send its data. Pipelining overlaps the blocks of a
data burst, which allows it to be partially transferred at the same time. TheChapter 8: Cache Memory^163