Digital Logic Fundamentals Unit 5 – Flip-Flops
Exercise 1 – Set/Reset Flip-Flop
EXERCISE OBJECTIVE
When you have completed this exercise, you will be able to demonstrate the operating
characteristics of a set/reset (RS) flip-flop by using cross-coupled NAND gates. You will verify
your results with an oscilloscope.
EXERCISE DISCUSSION
- A set/reset (RS) flip-flop has two inputs, S (SET) and R (RESET), and two complementary
outputs, Q and Q.
- The circles at S and R indicate that a logic low is required.
- This RS flip-flop does not require a clock signal; however, some RS flip-flops are configured
with a clock input. - A logic low at input S combined with a logic high at R sets the Q output to logic high and the
Q output to logic low.
- When the inputs are changed to a high at S and a low at R, the flip-flop is reset: output Q
becomes low and Q becomes high.
- An RS flip-flop is bi-stable because the outputs are latched, or stored, until switched to the
complement logic states. - The RS flip-flop consists of two NAND gates with cross-coupled outputs: one input connects
to the output of the adjacent gate. - The NAND gates in an RS flip-flop schematic are usually represented by the symbols for OR
gates with negated inputs. - An OR gate with negated inputs has the same output states as a NAND gate.
- Because Q connects to input B1 of NAND gate B, the two high inputs to gate B cause a low
at Q.
• Because Q connects to input A2 of NAND gate A, input A2 is low.
- When the RS flip-flop is set, the Q output is high.
• When the switch is open, the Q output remains high and the Q output remains low because
the gates are cross-coupled.• The feedback from gate B (Q) maintains input A2 low, and the feedback from gate A (Q)
maintains input B1 high.- NAND gate A has a low input that is required for a high output (Q), and NAND gate B has
two high inputs that are required for a low output (Q).
• The RS flip-flop latches to the SET condition (high Q and low Q) until the switch is placed
in the RESET position.