Digital Logic Fundamentals Unit 5 – Flip-Flops
- Placing the switch to RESET (R) puts a low at input B2. A low at either input of NAND gate
B causes a high output (Q).
• Because Q connects to input A2 of NAND gate A, the two high inputs at gate A cause a low
output (Q).- Because Q connects to input B1 of NAND gate B, input B1 is low.
• When the RS flip-flop is reset, the Q output is low and the Q output is high.
• When the switch is open, output Q remains high and output Q remains low because of the
feedback.• NAND gate B has a low input that is required for a high output (Q), and NAND gate A has
two high inputs that are required for a low output (Q).• The RS flip-flop latches to the RESET condition (high Q and low Q) until the switch is
placed in the SET position.- When the position of a switch changes, it bounces (makes and breaks contact) a few times
before making permanent contact.
• Because the Q and Q outputs of an RS flip-flop become latched to a fixed state at initial
switch contact to SET or RESET, switch bouncing does not affect the flip-flop output state.- An RS flip-flop buffers a circuit from the effect of switch bouncing; the RS flip-flop can be
used to debounce a switch contact.
• Switch bouncing does not change the RS flip-flop output state because Q and Q become
latched on initial contact to SET or RESET, and the NAND gates are cross-coupled.- A high at the SET and RESET inputs (1,1) after setting or resetting the flip-flop represents
placing the switch in the open position. - Placing the switch in the open position after SET or RESET does not change the output state.
- This RS flip-flop circuit cannot have a low at the SET and RESET inputs simultaneously
because of the switch arrangement.
• However, if a low were put at both the SET and RESET inputs, Q and Q would be high. This
state is prohibited because complementary outputs are desired.- Putting a high to the SET and RESET inputs following the prohibited output state (two
highs) causes a race condition between the Q and Q outputs to an indeterminate
complementary output condition.- Putting a low at the SET and RESET inputs is prohibited in an RS flip-flop circuit because