Chapter 11
Bit 3 (ADDEN) enables the address-detect feature used with 9-bit data.
Bit 2 (FERR) is set to 1 on detecting a framing error, which occurs on detecting
a logic-low Stop bit at the RX pin.
Bit 1 (OERR) is set to 1 on detecting an overrun error. The error occurs when
RCREG holds two unread bytes and the RSR detects the Stop bit of a new
received word. The RSR has nowhere to load the new byte, so the byte and any
data that follows while OERR is set is lost. Firmware is responsible for reading
bytes from RCREG frequently enough to prevent overrun errors. Hardware
flow control can help by de-asserting the flow-control output when RCREG is
full. To clear OERR, set CREN = 0. Then set CREN = 1 to re-enable receiving
data.
Bit 0 (RX9D) holds the ninth bit of received data when RX9 = 1. If the bit is a
parity bit, firmware is responsible for reading the bit and detecting parity errors.!
6
The serial port’s bit rate depends on a variety of register settings and the fre-
quency of the CPU’s clock source, or FOSC. The chips support multiple oper-
ating modes that can use different clock sources to conserve power when
possible.& 5
5
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The Baud Rate Control Register (BAUDCON) contains bits that relate to
enhanced features of the chip’s bit-rate generator for serial communications.
Bit 7 (ABDOVF) = 1 when a rollover has occurred while in auto-baud detect
mode. Firmware must clear the bit.
Bit 6 (RCIDL) = 1 when the receiver is idle (no receive operation is in
progress).
Bit 5 (RXDTP) sets the polarity for received data as inverted (1) or
non-inverted (0).
Bit 4 (TXCKP) sets the polarity for the idle state as low (1) or high (0).
Bit 3 (BRG16) determines whether to use an eight (0) or sixteen (1) bit value to
set the bit rate. In general, 16 bits enables greater accuracy in selecting rates.
Bit 2 is unimplemented and reads zero.
Bit 1 (WUE) is set to 1 to cause the EUSART to trigger an interrupt on a fall-
ing edge at RX. The interrupt can wake the chip from Sleep mode.