Consoles 959ever-so-slightly-exactly-not-quite on the same frequen-
cies, from their own independent clocks. Mixing such is
a disaster.
SRCs allow sources with a wide range of sample
rates to be reclocked to the console’s master clock,
allowing them to be processed normally. Being that they
use internally very long FIR filters and of varying
length depending on the ratio of input-to-output rate
conversion, they not only have latency, but it changes
too. Another slight shortcoming is the tendency to affect
the ultimate dynamic range by leaving artifacts way
down in level, but most current parts are excellent in
this regard. All in all, they are a near miracle-cure for
what was an intractable problem.25.19 Digital Signal ProcessorsThere are a number of features that distinguish devices
specifically designed for DSP from the admittedly
bigger and faster but generally dumber and seriously
more expensive behemoths powering PCs and the like.25.19.1 Multiplier/Accumulator (MAC)The heart of a DSP device is the hardware multiplier in
its arithmetic logic unit. This takes two full data-width
numbers, multiplies them, and leaves the result in an
accumulator, quickly. Further products of multiplica-
tions can be arranged by a software instruction called a
MAC, Multiply/ACcumulate, to be added to results
previously stored in the accumulator. The MAC is
central to DSP. Nearly every manipulation of a signal in
the digital domain is ultimately achieved by multiplying
a sample by another value, called the coefficient. The
simplest example is that of level control—in audio
terms, gain control. If an incoming sample is multiplied
by a value of 1, the result lodged in the accumulator is
the same as the input sample. If the gain-defining coef-
ficient is greater or less than 1, the accumulated result is
correspondingly greater or smaller than the input
sample.
The accumulator necessarily needs to be of a wider
word width than the input byte width capability since a
multiplication can end up with a much bigger or smaller
number than the input sample; in the case of the very
popular fixed-point Freescale (see Motorola) 56300
series DSP chips, the bus width (input-output word
width) is 24 bits while the accumulator widths are
56 bits. It’s a worthwhile rule of thumb—a multiplica-
tion results in double the bit width.
In this volume-control example, the input analog
signal is sampled at the front end of the encoder, an A/D
conversion is performed, and this value is deposited on
the DSP chip bus at its command. The input word is
multiplied by a coefficient, similarly picked up off the
data bus, and the result left in the accumulator.
Rounding off fits the possibly too long result to the
width of the DAC (e.g., down to 16 bits from a possible
maximum result of 32 bits from one 16 bit multiply).
The answer is put on the bus to be picked off at
command by the D/A convertor. The D/A performs a
near-instantaneous conversion back to analog, ready for
consumption by the real world. This whole routine is
repeated 48,000 times a second; each operation has less
than about 20Ps to take place. Congratulations! This is
the digital replacement for a $5 potentiometer.
To get a sense of the great strength of the digital
solution, Fig. 25-129A shows many A/D and D/A
converters hanging on the DSP input-output bus. Each
of these is independently addressable by the DSP chip;
it can systematically pick an input signal word from any
A/D, work on it, then deposit the result into any D/A
converter. Further, it can take input samples from any or
all of the A/Ds, multiply them in differing degrees
according to differing coefficients, and add the results
progressively within the accumulator. This accumu-
lated result is then scaled and passed to a D/A. In effect,
this is the digital equivalent of mixing a number of
sources, all the sources at different gain settings, to one
output.
The comparatively simple digital arrangement can be
made to equate to an analog soft matrix, as drawn in
Fig. 25-129B. It’s starting to look more like a viable
cost and space saving replacement; this small example
of six-in and six-out is already equivalent to 36 VCAs.
More inputs and more outputs to and from the mix
stage are of course possible. The principal limitations
are accumulator width, which is taken care of by
building in adequate head room just as one does in
analog, but more importantly processor time; after all, it
still has to do all the input-to-output multiplies within a
20.8Ps window.25.19.2 Instruction CyclesA processor instruction cycle is simplistically the time it
takes to perform one single simple operation, such as a
bus access (to acquire or dispose of data), an arithmetic
function or a move of data from a register to elsewhere.
Multiplies can take a bit longer, depending on the chip,
but DSP chip architectures with hardware multipliers
are very slick and time efficient. They need to be. The
processor speed determines how many of these clock
cycles are available for processing in a given time