Handbook for Sound Engineers

960 Chapter 25

window and so directly limits how much work the
processor can do. For example, a 200 Meg device has a
processor cycle rate of 200,000,000 Hz. Given a 48 kHz
sampling rate, this gives a maximum of just over 4000
cycles per sample period. Some operations can take
more than just one clock cycle, so this is an outside

ideal figure. In practice, it works out at somewhat fewer.

Although it looks like a big number, it seems vanish-

ingly small as soon as anything clever is attempted with

the DSP. This, above all else, is the primary reason why

upping the sample rate above the bare possible

minimum is a very unpopular notion in DSP circles.

Cycle budgets rule.

25.19.3 Processor Types

Specific DSP devices are chosen for a wide variety of

reasons, both real and perceived. Device flexibility,

per-unit cost, and ease of implementation (in the forms

of support from the manufacturer and quality of the

design tools) all factor in. In very large run products

such as consumer items, part cost will probably override

everything else while ease and speed of implementation

tend to be more important in lower-volume, high-

tweak-factor arenas such as pro-audio. Rarely is there

one overweaning performance feature that makes or

breaks a choice. However, since in order to squeeze the

most processing from each device a considerable

amount of their programming is still at the

machine-code level, the designer’s familiarity with a

particular assembler language can have a strong influ-

ence—this definitely falls into the ease and speed of

implantation department.

Perhaps the minimum for processing audio data is a

24 bit word width and correspondingly wider accumula-

tors and registers. As such the Freescale devices just

about fit the bill. They are fixed point processors, which

directly limits their dynamic range to the number of bits

(144 dB for 24 bits, 336 dB for the accumulators); fortu-

nately, this is plenty for most real-world audio

processing. Some applications, like some filters, demand

wider immediate dynamic ranges in their calculation and

intermediate-value data storage, and for those instances

long or double-precision arithmetic is used. The down

side is that such filters can take up to twice as long

(twice as many cycles) to calculate as single precision.

25.19.4 Floating Point

Floating point processors (floaters) as exemplified by

Analog Device’s “Sharc” series avoid this problem by

representing numbers internally in exponent/mantissa

format, having far more involved internal processing to

handle the complexity of dealing with these numbers.

The Sharcs can be operated as either 32 bit fixed point

or 32 bit floating point. Since the dynamic range of a

floater is as good as infinite regardless, none of the

dancing around one sometimes has to do with a fixed

Figure 25-129. A digital mix of a number of sources.

DSP

Program

memory

A/D 1

A/D 2

A/D 3

A/D 4

A/D 5

A/D 6

D/A 1

D/A 2

D/A 3

D/A 4

D/A 5

D/A 6

DPS bus

Data

memory

Analog inputs Analog outputs

A. Multiple level controls using DSP.

Input buffers

Output summing amps

B. Analog equivalent.