Reverse Engineering for Beginners

CHAPTER 12. CONDITIONAL JUMPS CHAPTER 12. CONDITIONAL JUMPS

12.5.3 MIPS.

Listing 12.36: Check for zero

BEQZ REG, label

Listing 12.37: Check for less than zero:

BLTZ REG, label

Listing 12.38: Check for equal values

BEQ REG1, REG2, label

Listing 12.39: Check for non-equal values

BNE REG1, REG2, label

Listing 12.40: Check for less than, greater than (signed)

SLT REG1, REG2, REG3
BEQ REG1, label

Listing 12.41: Check for less than, greater than (unsigned)

SLTU REG1, REG2, REG3
BEQ REG1, label

12.5.4 Branchless.

If the body of a condition statement is very short, the conditional move instruction can be used: MOVcc in ARM (in ARM
mode), CSEL in ARM64, CMOVcc in x86.

ARM

It’s possible to use conditional suffixes in ARM mode for some instructions:

Listing 12.42: ARM (ARM mode)

CMP register, register/value
instr1_cc ; some instruction will be executed if condition code is true
instr2_cc ; some other instruction will be executed if other condition code is true
... etc...

Of course, there is no limit for the number of instructions with conditional code suffixes, as long as the CPU flags are not
modified by any of them.

Thumb mode has the IT instruction, allowing to add conditional suffixes to the next four instructions. Read more about
it:17.7.2 on page 248.

Listing 12.43: ARM (Thumb mode)

CMP register, register/value
ITEEE EQ ; set these suffixes: if-then-else-else-else
instr1 ; instruction will be executed if condition is true
instr2 ; instruction will be executed if condition is false
instr3 ; instruction will be executed if condition is false
instr4 ; instruction will be executed if condition is false

12.6 Exercise

(ARM64) Try rewriting the code in listing.12.23by removing all conditional jump instructions and using theCSELinstruction.