APPENDIX A. X86 APPENDIX A. X86
Bit Abbreviation (meaning) Description
0 IM (Invalid operation Mask)
1 DM (Denormalized operand Mask)
2 ZM (Zero divide Mask)
3 OM (Overflow Mask)
4 UM (Underflow Mask)
5 PM (Precision Mask)
7 IEM (Interrupt Enable Mask) Exceptions enabling, 1 by default (disabled)
8, 9 PC (Precision Control)
00 — 24 bits (REAL4)
10 — 53 bits (REAL8)
11 — 64 bits (REAL10)
10, 11 RC (Rounding Control)
00 — (by default) round to nearest
01 — round toward−∞
10 — round toward+∞
11 — round toward 0
12 IC (Infinity Control) 0 — (by default) treat+∞and−∞as unsigned
1 — respect both+∞and−∞
The PM, UM, OM, ZM, DM, IM flags define if to generate exception in the case of a corresponding error.
A.3.2 Status Word
Read-only register.
Bit Abbreviation (meaning) Description
15 B (Busy) Is FPU do something (1) or results are ready (0)
14 C3
13, 12, 11 TOP points to the currently zeroth register
10 C2
9 C1
8 C0
7 IR (Interrupt Request)
6 SF (Stack Fault)
5 P (Precision)
4 U (Underflow)
3 O (Overflow)
2 Z (Zero)
1 D (Denormalized)
0 I (Invalid operation)The SF, P, U, O, Z, D, I bits signal about exceptions.
About the C3, C2, C1, C0 you can read more here: (17.7.1 on page 220).
N.B.: When ST(x) is used, the FPU addsxto TOP (by modulo 8) and that is how it gets the internal register’s number.
A.3.3 Tag Word.
The register has current information about the usage of numbers registers.
Bit Abbreviation (meaning)
15, 14 Tag(7)
13, 12 Tag(6)
11, 10 Tag(5)
9, 8 Tag(4)
7, 6 Tag(3)
5, 4 Tag(2)
3, 2 Tag(1)
1, 0 Tag(0)Each tag contains information about a physical FPU register (R(x)), not logical (ST(x)).
For each tag: