APPENDIX A. X86 APPENDIX A. X86
- 00 — The register contains a non-zero value
- 01 — The register contains 0
- 10 — The register contains a special value (NAN^2 ,∞, or denormal)
- 11 — The register is empty
A.4 SIMD registers
A.4.1 MMX registers.
8 64-bit registers: MM0..MM7.
A.4.2 SSE and AVX registers.
SSE: 8 128-bit registers: XMM0..XMM7. In the x86-64 8 more registers were added: XMM8..XMM15.
AVX is the extension of all these registers to 256 bits.
A.5 Debugging registers.
Used for hardware breakpoints control.
- DR0 — address of breakpoint #1
- DR1 — address of breakpoint #2
- DR2 — address of breakpoint #3
- DR3 — address of breakpoint #4
- DR6 — a cause of break is reflected here
- DR7 — breakpoint types are set here
A.5.1 DR6
Bit (mask) Description
0 (1) B0 — breakpoint #1 was triggered
1 (2) B1 — breakpoint #2 was triggered
2 (4) B2 — breakpoint #3 was triggered
3 (8) B3 — breakpoint #4 was triggered
13 (0x2000) BD — modification attempt of one of the DRx registers.
may be raised if GD is enabled
14 (0x4000) BS — single step breakpoint (TF flag was set in EFLAGS).
Highest priority. Other bits may also be set.
15 (0x8000) BT (task switch flag)N.B. A single step breakpoint is a breakpoint which occurs after each instruction. It can be enabled by setting TF in EFLAGS
(A.2.19 on page 881).
A.5.2 DR7
Breakpoint types are set here.
(^2) Not a Number