VHDL Programming

Predefined Attributes 161

One restriction on the use of these attributes is that they cannot be

used within a subprogram. A compiler error message results if a signal

kind attribute is used within a subprogram.

There are four attributes in the signal kind category:

s’DELAYED [(time)], which creates a signal of the same type as

the reference signal that follows the reference signal, delayed by

the time of the optional time expression

s’STABLE [(time)], which creates a boolean signal that is true

whenever the reference signal has had no events for the time

specified by the optional time expression

s’QUIET [(time)], which creates a boolean signal that is true

whenever the reference signal has had no transactions or events

for the time specified by the optional time expression

s’TRANSACTION, which creates a signal of type BITthat toggles its

value for every transaction or event that occurs on s

Attribute ’DELAYED

Attribute ’DELAYEDcreates a delayed version of the signal that it is attached

to. The same functionality can be obtained using a transport-delayed sig-

nal assignment. The difference between a transport-delay assignment and

the ’DELAYEDattribute is that the designer has to do more bookkeeping

with the transport signal assignment method. With a transport signal as-

signment, a new signal must be declared.

Let’s look at one use for the ’DELAYEDattribute. One method for mod-

eling ASIC devices is to place path-related delays on the input pins of the

ASIC library part. An example of this method is shown in Figure 6-2.

Typically, before the layout process, educated guesses are made for the

delays of each input. After layout, the real delay values are back-annotated

to the model, and the simulation is run again with the real delays. One

method to provide for back annotation of the delay values is to use generic

values specified in the configuration for the device. (Configurations are dis-

cussed in Chapter 7,“Configurations.”) A typical model for one of the and2

gates shown in Figure 6-2 might look like this:

LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;

ENTITY and2 IS

GENERIC ( a_ipd, b_ipd, c_opd : TIME );