VHDL Programming

162 Chapter Six

c_opd

a_ipd

b_ipd

a_ipd

b_ipd

a_ipd

b_ipd

c_opd

c_opd

c_opd

and2

and2

and2

Figure 6-2
Gate Array Logic
with Input and Out-
put Delays.

PORT ( a, b : IN std_logic;

c: OUT std_logic);

END and2;

ARCHITECTURE int_signals OF and2 IS

SIGNAL inta, intb : std_logic;

BEGIN

inta <= TRANSPORT a AFTER a_ipd;

intb <= TRANSPORT b AFTER b_ipd;

c <= inta AND intb AFTER c_opd;

END int_signals;

ARCHITECTURE attr OF and2 IS

BEGIN

c <= a’DELAYED(a_ipd) AND b’DELAYED(b_ipd) AFTER c_opd;

END attr;

In the preceding example, two architectures for entity and2show two

different methods of delaying the input signals by the path delay. The first

method uses transport-delayed internal signals to delay the input signals.

These delayed signals are then ANDed together and assigned to output

port c.

The second method makes use of the predefined signal attribute

’DELAYED. Input signals aand bare delayed by the path delay generic value

a_ipd(ainput path delay) and b_ipd(binput path delay). The values of

the delayed signals are ANDed together and assigned to output port c.