Configurations 175
END IF;
END IF;
data_out <= count;
END PROCESS;
END count_255;ARCHITECTURE count_64k OF counter IS
BEGIN
PROCESS(clk)
VARIABLE count : INTEGER := 0;
BEGIN
IF clear = ‘ 1 ’ THEN
count := 0;
ELSIF load = ‘ 1 ’ THEN
count := data_in;
ELSE
IF (clk’EVENT) AND (clk = ‘ 1 ’) AND
(clk’LAST_VALUE = ‘ 0 ’) THEN
IF (count = 65535) THEN
count := 0;
ELSE
count := count + 1;
END IF;
END IF;
END IF;
data_out <= count;
END PROCESS;
END count_64k;CONFIGURATION small_count OF counter IS
FOR count_255
END FOR;
END small_count;CONFIGURATION big_count OF counter IS
FOR count_64k
END FOR;
END big_count;This example shows how two different architectures for a counter
entity can be configured using two default configurations. The entity for the
counter does not specify any bit width for the data to be loaded into
the counter or data from the counter. The data type for the input and output
data is INTEGER. With a data type of integer, multiple types of counters can
be supported up to the integer representation limit of the host computer
for the VHDL simulator.
The two architectures of entity counter specify two different-sized
counters that can be used for the entity. The first architecture,count_255,
specifies an 8-bit counter. The second architecture,count_64k, specifies a