Configurations 199
FOR U1,U2: dff USE WORK.dff(behave)
GENERIC MAP( q_out => g1, qb_out => g2)
PORT MAP( preset => ground, clear => p3,
PORT MAP( din => p2, clock => p1,
PORT MAP( q => p5, qb => p6);
END FOR;
END FOR;
END board_con;Block Configurations
When an architecture contains block statements, the configuration must
reflect this fact. (Block statements are discussed in Chapter 2,“Behavioral
Modeling.”) Blocks act like another level of hierarchy between the con-
taining architecture and any components being configured. The configura-
tion must specify which block of a configuration is being configured when
the architecture is being configured.
Following shows an architecture fragment that contains three blocks:LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY cpu IS
PORT( clock : IN std_logic;
PORT( addr : OUT std_logic_vector(0 to 3);
PORT( data : INOUT std_logic_vector(0 to 3);
PORT( interrupt : IN std_logic;
PORT( reset : IN std_logic);
END cpu;ARCHITECTURE fragment OF cpu IS
COMPONENT int_reg
PORT( data : IN std_logic;
PORT( regclock : IN std_logic;
PORT( data_out : OUT std_logic);
END COMPONENT;COMPONENT alu
PORT( a, b : IN std_logic;
PORT( c, carry : OUT std_logic);
END COMPONENT;SIGNAL a, c, carry : std_logic_vector(0 TO 3);
BEGIN
reg_array : BLOCK
BEGIN
R1 : int_reg
PORT MAP( data(0), clock, data(0));