200 Chapter Seven
R2 : int_reg
PORT MAP( data(1), clock, data(1));R3 : int_reg
PORT MAP( data(2), clock, data(2));R4 : int_reg
PORT MAP( data(3), clock, data(3));END BLOCK reg_array;shifter : BLOCK
BEGIN
A1 : alu
PORT MAP( a(0), data(0), c(0), carry(0));A2 : alu
PORT MAP( a(1), data(1), c(1), carry(1));A3 : alu
PORT MAP( a(2), data(2), c(2), carry(2));A4 : alu
PORT MAP( a(3), data(3), c(3), carry(3));shift_reg : BLOCK
BEGIN
R1 : int_reg
PORT MAP( data, shft_clk, data_out);END BLOCK shift_reg;
END BLOCK shifter;
END fragment;The architecture consists of three blocks, each containing component
instantiations. The first block contains four int_regcomponents, and the
second contains an alucomponent, plus another BLOCKstatement. The last
block contains a single int_regcomponent.
The configuration for this architecture must take into account the fact
that BLOCKstatements exist in the architecture. Following is a simple
configuration for the architecture:CONFIGURATION cpu_con OF cpu IS
FOR fragment
FOR reg_array
FOR ALL: int_reg USE CONFIGURATION WORK.int_reg_con;
END FOR;
END FOR;