206 Chapter Eight
Overloading
Overloading allows the designer to write much more readable code. An
object is overloaded when the same object name exists for multiple sub-
programs or type values. The VHDL compiler selects the appropriate
object to use in each instance.
In VHDL, a number of types of overloading are possible. Subprograms
can be overloaded, operators can be overloaded, and enumeration types can
be overloaded. Overloading subprograms allows subprograms to operate
on objects of different types. Overloading an operator allows the oper-
ator to perform the same operation on multiple types. Overloading frees
the designer from the necessity of generating countless unique names for
subprograms that do virtually the same operation. The result of using
overloaded subprograms and operators is models that are easier to read
and maintain.Subprogram Overloading
Subprogram overloading allows the designer to write multiple subprograms
with the same name, but the number of arguments, the type of arguments,
and return value (if any) can be different. The VHDL compiler, at compile
time, selects the subprogram that matches the subprogram call. If no sub-
program matches the call, an error is generated.
The following example illustrates how a subprogram can be overloaded
by the argument type:LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
PACKAGE p_shift IS
TYPE s_int IS RANGE 0 TO 255;
TYPE s_array IS ARRAY(0 TO 7) OF std_logic;FUNCTION shiftr( a : s_array) return s_array;
FUNCTION shiftr( a : s_int) return s_int;
END p_shift;PACKAGE BODY p_shift IS
FUNCTION shiftr( a : s_array) return s_array IS
VARIABLE result : s_array;
BEGIN
FOR i IN a’RANGE LOOP
IF i = a’HIGH THEN
result(i) := ‘ 0 ’;