Chapter 16 Place and Route

This chapter discusses the process of implementing the

synthesis netlist of the CPU design into a target FPGA

device. The place and route tools read the netlist, extract

the components and nets from the netlist, place the compo-

nents on the target device, and interconnect the components

using the specified interconnections. After the place and

route process is complete, the designer has an imple-

mentation of the design in the target technology. The im-

plementation still needs to be verified for logical and tim-

ing correctness.

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