-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd,
CLK_ipd)-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := ‘ 0 ’;
VARIABLE TimingData_D_CLK : VitalTimingDataType :=
VitalTimingDataInit;-- functionality results
VARIABLE Violation : STD_ULOGIC := ‘ 0 ’;
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(1 to 6) ;
VARIABLE D_delayed : STD_ULOGIC := ‘U’;
VARIABLE CLK_delayed : STD_ULOGIC := ‘U’;
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) :=
(others => ‘X’);-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;CONSTANT DFF_Q_tab : VitalStateTableType := (
-- Violation, CLRN_ipd, CLK_delayed, D_delayed, PRN_ipd,
CLK_ipd
( L, L, x, x, x, x, x, L ),
( L, H, L, H, x, H, x, H ),
( L, H, H, x, H, x, x, S ),
( L, H, x, x, L, x, x, H ),
( L, H, x, x, H, L, x, S ),
( L, x, L, L, H, H, x, L ) );begin------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => “D”,
RefSignal => CLK_ipd,
RefSignalName => “CLK”,
SetupHigh => tsetup_D_CLK_noedge_
posedge,
SetupLow => tsetup_D_CLK_noedge_
posedge,
HoldHigh => thold_D_CLK_noedge_
posedge,
HoldLow => thold_D_CLK_noedge_
posedge,390 Chapter Seventeen