Behavioral Modeling 23
ARCHITECTURE buf OF buf IS
BEGIN
b <= a AFTER 20 ns;
END buf;Transport Delay Model
Following is an example of a transport delay model. It is similar in every
respect to the inertial delay model except for the keyword TRANSPORTin
the signal assignment statement to signal b. When this keyword exists,
the delay type used in the statement is the transport delay mechanism:LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY delay_line IS
PORT ( a : IN std_logic;
PORT ( b : OUT std_logic);
END delay_line;ARCHITECTURE delay_line OF delay_line IS
BEGIN
b <= TRANSPORT a AFTER 20 ns;
END delay_line;Simulation Deltas
Simulation deltas are used to order some types of events during a simu-
lation. Specifically, zero delay events must be ordered to produce con-
sistent results. If zero delay events are not properly ordered, results can
be disparate between different simulation runs. An example of this is
shown using the circuit shown in Figure 2-6. This circuit could be part of
a clocking scheme in a complex device being modeled. It probably would
not be the entire circuit, but only a part of the circuit used to generate
the clock to the D flip-flop.
The circuit consists of an inverter, a NAND gate, and an AND gate
driving the clock input of a flip-flop component. The NAND gate and AND
gate are used to gate the clock input to the flip-flop.
Let’s examine the circuit operation, using a delta delay mechanism and
another mechanism. By examining the two delay mechanisms, we will
better understand how a delta delay orders events.