VHDL Programming

24 Chapter Two

D

CLK

Q

QB

DFF

A

Clock

C

D

B

E

F

Figure 2-6
Simulation Delta
Circuit.

To use delta delay, all of the circuit components must have zero delay

specified. The delay for all three gates is specified as zero. (Real circuits

do not exhibit such characteristics, but sometimes modeling is easier if

all of the delay is concentrated at the outputs.) Let’s examine the non-

delta delay mechanism first.

When a falling edge occurs on signal A, the output of the inverter

changes in 0 time. Let’s assume that such an event occurs at time 10

nanoseconds. The output of the inverter, signal B, changes to reflect the

new input value. When signal B changes, both the AND gate and the

NAND gate are reevaluated. For this example, the clock input is assumed

to be a constant value ‘ 1 ’. If the NAND gate is evaluated first, its new

value is ‘ 0 ’.

When the AND gate evaluates, signal B is a ‘ 0 ’, and signal C is a ‘ 1 ’;

therefore, the AND gate predicts a new value of ‘ 0 ’. But what happens

if the AND gate evaluates first? The AND gate sees a ‘ 1 ’value on signal

B, and a ‘ 1 ’value on signal C before the NAND gate has a chance to

reevaluate. The AND gate predicts a new value of ‘ 1 ’.