34 Chapter Two
END BLOCK BLK1;
In this example, signal qbusis declared in two blocks. The interesting
feature of this model is that one of the blocks is contained in the other. It
would seem that BLK2has access to two signals called qbus—the first from
the local declaration of qbusin the declaration section of BLK2and the
second from the declaration section of BLK1. BLK1is also the parent block
of BLK2. However, BLK2sees only the qbussignal from the declaration in
BLK2. The qbussignal from BLK1has been overridden by a declaration of the
same name in BLK2.
The qbussignal from BLK1can be seen inside of BLK2, if the name of
signal qbusis qualified with the block name. For instance, in this example,
to reference signal qbusfrom BLK1, use BLK1.qbus.
In general, this can be a very confusing method of modeling. The
problem stems from the fact that you are never quite sure which qbusis
being referenced at a given time without fully analyzing all of the decla-
rations carefully.
As mentioned earlier, blocks are self-contained regions of the model.
But blocks are unique because a block can contain ports and generics.
This allows the designer to remap signals and generics external to the
block to signals and generics inside the block. But why, as designers,
would we want to do that?
The capability of ports and generics on blocks allows the designer to
reuse blocks written for another purpose in a new design. For instance,
let’s assume that you are upgrading a CPU design and need extra func-
tionality in the ALU section. Let’s also assume that another designer has
a new ALU model that performs the functionality needed. The only trou-
ble with the new ALU model is that the interface port names and generic
names are different than the names that exist in the design being upgraded.
With the port and generic mapping capability within blocks, this is no
problem. Map the signal names and the generic parameters in the design
being upgraded to ports and generics created for the new ALU block.
Following is an example illustrating this:PACKAGE math IS
TYPE tw32 IS ARRAY(31 DOWNTO 0) OF std_logic;
FUNCTION tw_add(a, b : tw32) RETURN tw32;
FUNCTION tw_sub(a, b : tw32) RETURN tw32;
END math;