VHDL Programming

Sequential Processing 59

then we know that a rising edge has occurred. Whenever a rising edge

occurs on signal clk, we need to check the setup time for a violation. If

the last transition on signal dwas less than 20 nanoseconds ago, then

the expression:

(NOW - last_D_change)

returns a value that is less than 20 nanoseconds. The ASSERTstatement

triggers and reports the assertion message setup violation as a warning

to the designer. If the last transition on signal doccurred more than 20

nanoseconds in the past, then the expression returns a value larger than

20 nanoseconds and the ASSERTstatement does not write out the message.

Remember, the ASSERTstatement writes out the message when the assert

condition is false.

The message reported to the user has, at a minimum, the user string

and the error classification. Some simulators also include the time of the

assertion report as well as the line number in the file of the assertion.

The ASSERTstatement used in this example was a sequential ASSERT

statement, because it was included inside a PROCESSstatement. A con-

current version of the ASSERTstatement also exists. It has exactly the

same format as the sequential ASSERTstatement and only exists outside

a PROCESSstatement or subprogram.

The concurrent ASSERTstatement executes whenever any signals that

exist inside of the condition expression have an event upon them. This is

as opposed to the sequential ASSERTstatement in which execution occurs

when the sequential ASSERTstatement is reached inside the PROCESS

statement or subprogram.

WAIT Statements

The WAITstatement gives the designer the ability to suspend the sequen-

tial execution of a process or subprogram. The conditions for resuming exe-

cution of the suspended process or subprogram can be specified by the

following three different means:

WAIT ONsignal changes

WAIT UNTILan expression is true

WAIT FORa specific amount of time