0195136047.pdf

6.2 DIGITAL SYSTEM COMPONENTS 301

0

Clock Q 2

0 0 0 1 1 1 1 0

0

Q 1

0 1 1 0 0 1 1 0

0

Q 0

1 0 1 0 1 0 1 0

T 1

T 2

T 3

T 4

T 5

T 6

T 7

T 8

(c)

1

Clock

Clear

1

1

(b)

1 1 1

111

0

0

00000

00 00

00 00 111

T 1

Q 0

Q 1

Q 2

T 2 T 3 T 4 T 5 T 6 T 7 T 8

Figure 6.2.5Continued

The slow speed of operation, caused by the long time required for changes in state to ripple
through the flip-flops, is a disadvantage of ripple counters. This problem is overcome by using
synchronous converters. However, additional control logic is needed to determine which flip-
flops, if any, must change state, since flip-flops are triggered simultaneously. Figure 6.2.6 shows
the logic diagram of a 3-bit binary synchronous converter using JKFFs. Synchronous counters
can be designed to cycle through any sequence of states. Variousn-bit synchronous converters
are commercially available as MSI packages. Some counters are also programmable.
Figure 6.2.7(a) shows a 4-bit (modulo-4) ring counter using D flip-flops; its timing diagram
is given in Figure 6.2.7(b). A modulo-nring counter requiresNflip-flops and no other gates,
whereas modulo-Nripple and synchronous counters need only log 2 Nflip-flops. However, ripple
and synchronous counters generally use more components than ring counters.

Clock

1 J 2

k 2

Ck 2

Q 2

Q 2

J 1

k 1

Ck 1

Q 1

Q 1

J 0

k 0

Ck 0

Q 0

Q 0

Figure 6.2.63-bit binary synchronous converter using JKFFs.

D 0

Clock

(a)

Ck 0

Q 0

Q 0

D 1

Ck 1

Q 1

Q 1

D 2

Ck 2

Q 2

Q 2

D 3

Ck 3

Q 3

Q 3

Figure 6.2.74-bit ring counter using D flip-flops.(a)Block diagram.(b)Timing diagram.