336 DIGITAL BUILDING BLOCKS AND COMPUTER SYSTEMS*6.2.12Show an arrangement for multiplexing 64-to-1 by
using four 16-to-1 multiplexers and one 4-to-1
multiplexer.
6.2.13Sketch the output waveforms for the register of
Figure 6.2.4(a) in the text if JKFFs are used in
place of D flip-flops.
6.2.14Show a block diagram of a 4-bit, parallel-input
shift-right register and briefly explain its opera-
tion.6.2.15Draw the timing diagram of Example 6.2.3 for a
4-bit shift-right register.
6.2.16Let the content of the register of Example 6.2.3 be
initially 0111. With data in being 101101, what is
the content of the register after six clock pulses?6.2.17A shift register can be used as a binary (a) divide-
by-2, and (b) multiply-by-2 counter. Explain.*6.2.18Show a block diagram of a 4-bit shift-right register
using JKFFs.
6.2.19Obtain a block diagram of a shift-left/right register
using D flip-flops.6.2.20Design a 4-bit universal shift register.
6.2.21(a) Show a block diagram of an SRFF connected
to store 1 bit.(b) Using 4 SRFFs obtain the block diagram for
an SISO shift register.(c) See what can be done to convert the SISO
device to SIPO.*6.2.22Draw a block diagram of a 4-bit PIPO register and
briefly describe its operation.
6.2.23Taking parallel data from a computer to be fed
out over a single transmission line needs a PISO
device. Develop a block diagram for such a shift
register and briefly explain its operation.
6.2.24Give a block diagram for a modulo-5 binary ripple
counter using JKFFs and draw its timing diagram.
6.2.25(a) For a JKFF withJK=11, the output changes
on every clock pulse. The change will be co-
incident with the clock pulse trailing edge and
the flip-flop is said to toggle, whenT=1, for
the T flip-flop. Show JKFF connected as a T
flip-flop and its timing diagram.(b) Using T flip-flops, show the block diagram for
a 3-bit ripple counter and its input and output
waveforms.6.2.26Sketch the timing diagram for a 4-bit ripple
counter which uses T flip-flops. (See Problem
6.2.25.)*6.2.27Counting to moduli other than 2nis a frequent
requirement, the most common being to count
through the binary-coded decimal (BCD) 8421 se-
quence. All that is required is a four-stage counter
which, having counted from 0000 to 1001 (i.e.,
decimal 0 to 9; ten states), resets to 0000 on the
next clock pulse. Develop a block diagram of an
asynchronous decade counterand show its timing
diagram.6.2.28Consider the synchronous counter shown in Figure
6.2.6 of the text.(a) Draw its timing diagram.(b) Show the implementation of the same syn-
chronous counter using D flip-flops.(c) Draw the timing diagram for part (b).
6.2.29Consider aseries-carry synchronous counterwith
T flip-flops shown in Figure P6.2.29 in which the
AND gates carry forward the transitions of the
flip-flops, thereby improving the speed. Sketch the
output waveform for the synchronous counter.6.2.30Figure P6.2.30 shows themod-8 counterwhich
counts from 0 10 to 7 10 before resetting. Explain
the operation of the counter and sketch the timing
diagram.6.2.31Counters are used to realize various dividers in
the schematic representation of the digital clock
shown in Figure P6.2.31. The blocks labeled
“logic array” are logic gate combinations required
to activate the corresponding segments in order to
display the digits.(a) Check to see that the six outputs (Y 0 through
Y 5 ) display the number of hours, minutes, and
seconds.(b) If the date is also to be displayed, suggest
additional circuitry.
*6.2.32Determine the bits required for a D/A converter to
detect 1-V change whenVref=15 V.