0195136047.pdf

PROBLEMS 337

Input pulses

(^1) T 0 Output
Ck
FF0
Y 0 T 1
Ck
FF1
Y 1 T 2
Ck
FF2
Y 2
Figure P6.2.29
1
Clock
input line
J
Ck
FF1
A
A(LSB)
J
Ck
FF2
B
B
J
K KK
Ck
FF3
C
C Figure P6.2.30
100:1
Divider
6 kHz
clock
Logic
array
Y 0 Y 1 Y 2 Y 3 Y 4 Y 5
Logic
array
Output to 7-segment display elements
Logic
array
Logic
array
Logic
array
Logic
array
60:1
Divider
10:1
Divider
6:1
Divider
10:1
Divider
6:1
Divider
10:1
Divider
Figure P6.2.31
6.2.33For the 4-bit D/A converter of Figure 6.2.9, calcu-
late:
(a) The maximum analog output voltage.
(b) The minimum analog output voltage.
(c) The smallest detectable analog output voltage
whenVref=−10 V.
6.2.34For the 4-bit weighted-resistor D/A converter
shown in Figure 6.2.9, prepare a table showing
decimal, binary equivalent, and currentIinin per
unit, where 1 pu=Vref/R. Also sketch the analog
output waveform, i.e.,Iinas a function of digital
binary input.
6.2.35For a 6-bit weighted-resistor D/A converter, ifRis
the resistor connected to the MSB, find the other
resistor values needed, and calculate the maximum
analog output voltage, the minimum analog output
voltage, and the smallest detectable analog output
voltage ifVref=−15 V.
6.2.36Analyze the 2-bitR–2Rladder-network D/A con-
verter, and corresponding to binary 01, 10, and 11,
obtain the equivalent circuits and determine the