FPGA_VIVADO_SI_VHDL_Mihael_Cristian_Ignat

w

end process;

uut: counter

Generic Map (number_of_bits => 8)

Port Map( clk => clk,

ce => ce,

r => r,

q => q);

end Behavioral;

VGA_pattern.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity VGA_pattern is
Port ( clk : in STD_LOGIC;
R : out STD_LOGIC_VECTOR (3 downto 0);
G : out STD_LOGIC_VECTOR (3 downto 0);
B : out STD_LOGIC_VECTOR (3 downto 0);
HAddr : out STD_LOGIC_VECTOR (11 downto 0);
VAddr : out STD_LOGIC_VECTOR (11 downto 0);
HSync : out STD_LOGIC;
VSync : out STD_LOGIC;
en_q : out STD_LOGIC);
end VGA_pattern;

architecture Behavioral of VGA_pattern is
component Sync_VGA
Port ( clk : in STD_LOGIC;
HSync : out STD_LOGIC;
HAddr : out STD_LOGIC_VECTOR (11 downto 0);
VSync : out STD_LOGIC;
VAddr : out STD_LOGIC_VECTOR (11 downto 0);
en_q : out STD_LOGIC);
end component;

signal HAddr_reg : STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
signal VAddr_reg : STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
signal en_q_reg : STD_LOGIC := '0';
begin