Physics and Engineering of Radiation Detection

8.7. Analog to Digital Conversion 501

Vin
Digital Output

Time

Figure 8.7.2: Counting cycles in a digital

ramp ADC.

Irregular Sampling. Since the counter keeps on counting until the DAC

output does not exceed the input voltage, the conversion time depends on the

height of the signal. This implies that the sampling is irregular for time varying

input signal, something which makes the readout timing and analysis difficult.

B.2 SuccessiveApproximationADC................

As we saw in the previous section, the digital ramp ADC suffers from slow speed since
the counter always starts from zero at the start of the conversion cycle. To overcome
this disadvantage the counting process must be modified. This can be accomplished
by replacing the binary counter by a successive approximation register (SAR) (see
Fig.8.7.3). This register is still a counter but it does not count up in binary sequence,
rather it increments the counts by trying all bits and comparing the result of DAC
output to the analog input at each step. It starts with the most significant bit and
ends its cycle with the least significant bit. At each step it sets the bits according
to whether the difference between DAC output and analog input is less than or
greater than zero. The advantage of this method is that the DAC output converges
to the analog input faster than the simple binary counter. Fig.8.7.4 shows typical
conversion iterations of a SAR.
The SAR provides an additional bit for the shift register to notify of its completion
of the conversion. This can also be a predefined regularly spaced clock cycle, in which
case the output is not irregularly spaced in time as in the digital ramp ADC.
The main drawback of successive approximation ADC is its high differential non-
linearity, which could go as high as 20

B.3 TrackingADC

Tracking ADC uses an up/down counter as opposed to a regular counter in digital
ramp ADC (see Fig.8.7.5). The counter counts continuously on a clock and counts
up or down according to whether the comparator output is high or low. In this
way the counter continuously tracks the input voltage and never gets reset unless
the input voltage itself drops to zero. The net effect is the fast conversion time and
simplicity in design as in this case the shift register is not needed. Fig.8.7.6 shows
how such an ADC tracks the input analog voltage.
The main disadvantage of this design is that the counter continuously counts up
or down and consequently the digitized output is never stable. This variation can,
however, be minimized by latching the counter output to a shift register only when
the output changes by some predefined value.