VHDL Programming

262 Chapter Ten This logic circuitry performs a prioritization of the presetsignal with respect to the clearsignal. Because the ...

VHDL Synthesis 263 END count_types; LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_unsigned.ALL; USE WORK.count_t ...

264 Chapter Ten counter. It is the process that is clocked by the clock and transfers the new calculated output count_valto the ...

Figure 10-9 A Sample Synthesized Output. shift_val(0) <= ‘ 0 ’; END IF; END PROCESS; current: PROCESS BEGIN WAIT UNTIL clk’EV ...

266 Chapter Ten The architecture is organized similarly to the last example, with two processes used to describe the functionali ...

VHDL Synthesis 267 PACKAGE vm_pack IS TYPE t_vm_state IS (main_st, review_st, repeat_st, TYPE t_vm_state IS (save_st, TYPE t_vm_ ...

13 2 Review Repeat Save Erase Main Send Address Record Begin Record Record Message 1 # # 2 # 5 # Figure 10-11 State Transition D ...

VHDL Synthesis 269 PROCESS(current_state, key) BEGIN play <= ‘ 0 ’; save <= ‘ 0 ’; erase <= ‘ 0 ’; recrd <= ‘ 0 ’; a ...

270 Chapter Ten END IF; WHEN record_st => IF (key = ‘ 5 ’) THEN next_state <= begin_rec_st; ELSE next_state <= record_s ...

VHDL Synthesis 271 The rest of the next state process consists of one CASEstatement. This CASEstatement describes the action to ...

272 Chapter Ten SUMMARY In this chapter, we looked at a number of different VHDL synthesis exam- ples. They ranged from simple g ...

CHAPTER 11 High-Level Design Flow This chapter describes the design flow used to create com- plex FPGA and ASIC devices. The des ...

274 Chapter Eleven Design Specification HDL Capture RTL Simulation RTL Synthesis Functional Gate Simulation Place and Route Post ...

High-Level Design Flow 275 signer creates the VHDL RTL description that describes the clock-by-clock behavior of the design. The ...

276 Chapter Eleven Create VHDL Compile VHDL Run RTL Simulation Results OK yes no Figure 11-2 RTL Simulation Flow. After the simu ...

High-Level Design Flow 277 Figure 11-3 Sample Waveform Output. has a lot of changes in a short amount of time and the signal val ...

278 Chapter Eleven Figure 11-4 Text Tabular Output. To synthesize a VHDL description, the designer reads the verified VHDL descr ...

High-Level Design Flow 279 determine whether or not the design looks reasonable. For most reason- able size designs, however, it ...

280 Chapter Eleven because each has a different-sized basic cell. In the preceding sample area report, the design produced 8 LC ...

High-Level Design Flow 281 NAME GATE ARRIVAL LOAD ————————————————————————————————————————————————————————————————————————————— ...