198 Chapter Seven
ation and the actual entity, then a mapping between the socket (compo-
nent instantiation) and the chip (actual entity) is needed.
The actual chip to be mapped is described by the entity and architecture
shown here:LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY dff IS
GENERIC( q_out, qb_out : time);
PORT( preset, clear, din,
PORT( clock : IN std_logic;
PORT( q, qb : OUT std_logic);
END dff;ARCHITECTURE behave OF dff IS
BEGIN
dff_proc : PROCESS(preset, clear, clock)
VARIABLE int_q : std_logic;
BEGIN
IF preset = ‘ 0 ’ and clear = ‘ 0 ’ THEN
IF (clock’EVENT) AND (clock = ‘ 1 ’) THEN
int_q := din;
END IF;ELSIF preset = ‘ 1 ’ AND clear = ‘ 0 ’ THEN
int_q := ‘ 1 ’;ELSIF clear = ‘ 1 ’ AND preset = ‘ 0 ’ THEN
int_q := ‘ 0 ’;ELSE
int_q := ‘X’;END IF;q <= int_q after q_out;int_q := not(int_q);
qb <= int_q after qb_out;END PROCESS dff_proc;
END behave;The names of the ports and generics are completely different than the
component declaration; therefore, mapping is required. Following is a
configuration that places the actual chip in the socket (maps the ports
and generics):CONFIGURATION board_con OF board IS
FOR structural