VHDL Programming

322 Chapter Thirteen

Process regprocis triggered when a rising edge occurs on input clk.

When the process is triggered, input ais copied to output q.

Regarray

The regarrayentity is used to model the set of registers within the CPU

that are used to store intermediate values during instruction processing.

These registers are read from and written to during the execution of

instructions. The set of registers is modeled as a RAM of eight 16-bit

words. The symbol for the regarrayentity is shown in Figure 13-8.

To write a location in the regarray, set input selto the location to be

written, input data with the data to be written, and put a rising edge on

input clk. To read a location from regarray, set input selto the location

to be read and set input ento a ‘ 1 ’; the data is output on port q.

The register array is modeled as two separate processes as shown in

the following:

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

use work.cpu_lib.all;

entity regarray is

port( data : in bit16;

port( sel : in t_reg;

port( en : in std_logic;

port( clk : in std_logic;

port( q : out bit16);

end regarray;

q

clk

data

en

sel

RegArray

Figure 13-8
RegArray Symbol.