VHDL Programming

18 Chapter Two

I0

I1

A B

Q

MUX4

I3

I2

Figure 2-2
Mux4 Symbol.

q <= i2 AFTER 10 ns WHEN 2,

q <= i3 AFTER 10 ns WHEN 3,

q <= ‘X’ AFTER 10 ns WHEN OTHERS;

sel <= 0 WHEN a = ‘ 0 ’ AND b = ‘ 0 ’ ELSE

1 WHEN a = ‘ 1 ’ AND b = ‘ 0 ’ ELSE

2 WHEN a = ‘ 0 ’ AND b = ‘ 1 ’ ELSE

3 WHEN a = ‘ 1 ’ AND b = ‘ 1 ’ ELSE

4 ;

END mux4;

The entity for this model has six input ports and one output port. Four

of the input ports (I0, I1, I2, I3) represent signals that will be assigned

to the output signal q. Only one of the signals will be assigned to the out-

put signal qbased on the value of the other two input signals aand b. The

truth table for the multiplexer is shown in Figure 2-3.

To implement the functionality described in the preceding, we use a

conditional signal assignment statement and a selected signal assignment.

The second statement type in this example is called a conditional signal

assignment statement. This statement assigns a value to the target sig-

nal based on conditions that are evaluated for each statement. The

statement WHENconditions are executed one at a time in sequential order

until the conditions of a statement are met. The first statement that

matches the conditions required assigns the value to the target signal.

The target signal for this example is the local signal sel. Depending

on the values of signals aand b, the values 0 through 4 are assigned

to sel.

If more than one statement’s conditions match, the first statement that