VHDL Programming

Running the simulation through the entire process verifies the func-

tionality of the placed and routed design. To verify the timing and

functionality, we need to back-annotate the timing from place and route

to the simulation.

Back-Annotated Simulation

To run timing back-annotated simulation, we don’t need to recompile. We

only need to specify to the simulator which SDF file to read. This is done

by the following command:

vsim -sdfmax /u1=cpuout.sdf topconstruct

This command tells the simulator to back-annotate the VITAL simu-

lation of the CPU design with SDF file cpuout.sdfcreated by the place

and route tools. After this command has executed, the simulation is

invoked, and the SDF file is back-annotated to component U1(cpu) and

simulation started. Running the simulation produces the waveform shown

in Figure 17-6.

The back-annotated delays are seen on the waveforms for addrand

dataaround time 400 nanoseconds. Notice that, instead of one transition,

the waveforms have a number of transitions that finally settle out. Using

this timing information, the designer can now increase the clock speed

CPU:Vital Simulation 397

Figure 17-6

Simulation

Waveform.