Sequential Processing 41
PORT( a, b : IN std_logic;
PORT( c : OUT std_logic);
END nand2;ARCHITECTURE nand2 OF nand2 IS
BEGIN
PROCESS( a, b )
VARIABLE temp : std_logic;
BEGIN
temp := NOT (a and b);IF (temp = ‘ 1 ’) THEN
c <= temp AFTER 6 ns;
ELSIF (temp = ‘ 0 ’) THEN
c <= temp AFTER 5 ns;
ELSE
c <= temp AFTER 6 ns;
END IF;END PROCESS;
END nand2;This example shows how to write a model for a simple two-input NAND
gate using a process statement. The USEstatement declares a VHDL pack-
age that provides the necessary information to allow modeling this NAND
gate with 9 state logic. (This package is described in Appendix A,“Stan-
dard Logic Package.”) We discuss packages later in Chapter 5,“Subpro-
grams and Packages.”The USEstatement was included so that the model
could be simulated with a VHDL simulator without any modifications.
The entity declares three ports for the nand2gate. Ports aand bare the
inputs to the nand2gate and port cis the output. The name of the ar-
chitecture is the same name as the entity name. This is legal and can save
some of the headaches of trying to generate unique names.
The architecture contains only one statement, a concurrent process
statement. The process declarative part starts at the keyword PROCESS
and ends at the keyword BEGIN. The process statement part starts at the
keyword BEGINand ends at the keywords END PROCESS. The process dec-
laration section declares a local variable named temp. The process state-
ment part has two sequential statements in it; a variable assignment
statement:temp := NOT (a AND b);and an IF THEN ELSEstatement:IF (temp = ‘ 1 ’) THEN