Microsoft Word - Digital Logic Design v_4_6a

4.5. Additional Flip Flops

 D flip-flop (or D-latch)
Although we have talked about SR flip-flop first, there are many other types of flip flops. Each have
their own set of advantages and disadvantages. D flip-flop is the most commonly used flip-flops due
to its simplicity. Additionally, D flip-flop does not have an inherent critical race.

SR flip-flops can be modified using NAND gates to create a D flip flop as shown in the following

diagram:

The D flip-flop may be referred to as “gated D Latch”, a transparent D latch, a level sensitive flip-flop

or data flip-flop. Symbol and Compressed Characteristic table is shown below:

Note: When C=0 (inactive), the last value of D is driving the output. Also it can be shown that it does

not contain critical race and is logic hazard free.

 Explore the specifications for 74LS373 “level activated” and 74LS374 “Positive-edge

triggered”. Refer to Course Website for the complete specifications including:

• Set up time (tsu)


• Hold time (th)


• Sampling interval, tsi = (tsu+ th)
  The Minimum tsi is required for proper operation of the circuit.


• 3-state output.

 Although there are pulse, level activated flip flop and edge-triggered D latches, it is recommended

that new design use edge-triggered flip-flops.

 Basic edge-triggered flip-flop

One ways to create a narrow pulse is by using the following circuit:

D flip-flop Symbol

D

C

Q

Q’

C D Q+

0 0 Q

0 1 Q

1 0 0

1 1 1

Compressed Characteristic

Table

Q=0 Q=1

C.D

C’ + D’

C.D’

C’ +D

State Diagram

∆t

(delay)

Q’

Q Q

+

Enable Control,

C

D set

reset