tpd_PRN_Q_negedge : VitalDelayType01 :=
DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 :=
DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 :=
DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType :=
DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType :=
DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType :=
DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType :=
DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01);port(
Q : out STD_LOGIC;
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC);
attribute VITAL_LEVEL0 of DFF : entity is TRUE;
end DFF;-- architecture body --architecture AltVITAL of DFF is
attribute VITAL_LEVEL1 of AltVITAL : architecture is
TRUE;SIGNAL D_ipd : STD_ULOGIC := ‘U’;
SIGNAL CLRN_ipd : STD_ULOGIC := ‘U’;
SIGNAL PRN_ipd : STD_ULOGIC := ‘U’;
SIGNAL CLK_ipd : STD_ULOGIC := ‘U’;begin---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
end block;
--------------------CPU:Vital Simulation 389