Microsoft Word - Digital Logic Design v_4_6a
Present State (PS/NS) Yi Yi+ Ji Ki Comment User for 1s (Set-Hold 1) Use for 0s (Clear-Hold 0) 0 0 0 1 1 0 1 1 0 - 1 - - 1 - 0 Ho ...
J2 = Y1’.Y2’.X’ + Y1’.Y2’.X + Y1.Y2’.X’ + Y1.Y2’.X = Y1’.Y2’ + Y1.Y2’ = Y2’ By observing all the clears (Y2 =1 Y2+=0), we can ...
5.6. FSM Design Examples Design a 3-bit up/down binary counter. Solution: Step 1 – State Diagram Describing the system Step 2 ...
Step 4 – Excitation Input and Output Equation Note: T= y (xor) y+ Present State Ext. Input Next State y 2 y 1 y 0 UD D 2 =y 2 + ...
Step 5 – Schematics 00 01 11 10 y 1 y 0 k 1 k 0 z 2 = y 2 += D 2 = y 1 y 0 k 1 k 0 00 01 11 10 00 01 11 10 y 1 y 0 k 1 k 0 00 01 ...
Design a 4-botton lock (red, blue, green and black) using T flip flop. The lock will open only when Red, Green,Black and Red b ...
Step 3 – Assign State variables and redraw state diagram Step 4 – Excitation Input and Output Equation Note: T= y (xor) y+ Prese ...
Step 5 – Schematics 00 01 11 10 y 1 y 0 k 1 k 0 T 0 = y 1 y 0 k 1 k 0 00 01 11 10 T 1 = 00 01 11 10 y 1 y 0 k 1 k 0 Open = 00 01 ...
Design the control for a video arcade game that cost $0.50 to play. Your design should accept quarter and nickel coins and hav ...
Design a vending machine control that accepts nickels, quarters and dollar bills. All products are priced at $1.00. User may s ...
5.7. Additional Resources Wakerly, I. Digital Design. (2006) Prentice Hall Chapter 8 “Sequential Logic Design Practices” ...
5.8. Problems Refer to http://www.EngrCS.com or online course page for complete solved and unsolved problem set. ...
Chapter 6. Finite State Machine Optimization & Testing 6.1. Key concepts and Overview State Minimization and FSM Design Pr ...
6.2. State Minimization and FSM Design Process The state minimization is done after the fourth step of the seven steps of Finite ...
6.3. State Minimization Using an Implication Chart (or Table) The Implication Chart Method is a systematic approach to find the ...
In general for an n-state machine, we will have (n^2 - n)/2 cells. Each of the cells in the implication chart relates State Sj w ...
After the application of previous two rules we will end up with the following table. Note: At this stage, many of the states hav ...
Second marking pass. Repeat the process with the resulting chart from the previous pass. In this pass, no change was made to t ...
indicates that the following states are equivalent: S 0 does not have equivalent, so it will need a new designator Y 0 state ...
6.4. Design for Testability (DFT) During the design phase, you need to consider the testing needs. Here are a few key types of t ...
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