Microsoft Word - Digital Logic Design v_4_6a
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BCD to 7-segment display driver Function: Binary Coded Decimal Digits (4 inputs “0-9”) 7 output “one per segment” Example:74 ...
Note: The output is active low and open collector: H, Inactive and OFF are same Active, L and ON are the same. In order to ligh ...
74LS47 ...
3.9. Programmable Logic Devices (PLDs) PLDs allow a designer to implement his/her design on a single chip. The main advantages o ...
(3) Erase ability Some devices allow the blown fuses to be re-fused by: (a) Ultraviolet Light (through a small window on the top ...
F(A 0 ,A 1 )= ∑(1,2), which means fuses 0 and 3 need to be blown. Example Draw the fuse map for the smallest PROM that impleme ...
Example Use a PROM to design a 4-byte memory that contain 10, 50, 90 and 20 in location 0 to 3. Show the system diagram and PR ...
Programmable Logic Arrays (PLA) PLAs are similar to PROMs with the added flexibility of programmable AND array connections. PL ...
Programmable Array Logic (PAL) or Generic Array Logic (GAL) PAL and GAL are two different way to refer to this technology. PAL ...
PALs or GALs are named based on the number of inputs and outputs (PALxxyzz) where: “xx” is the number of maximum AND array i ...
Benefits of PLDs over individual gates: Shorter design time (rapid prototype). Allow for rapid design changes. Decreased PC b ...
(a) A=A(H)=AL)( =A(H)=AL)( (b) A=A(H)=A(H)=A(H)=AL)( (2) To fully specify a circuit, you need to provide a Signal List (SL) in a ...
3.10. Additional Resources Wakerly, I. Digital Design. (2006) Prentice Hall Chapter 6 “Combinational Logic Design Practices” ...
3.11. Problems Refer to http://www.EngrCS.com or online course page for complete solved and unsolved problem set. ...
Chapter 4. Introduction to Feedback Circuits and Sequential Logic Analysis This is the first section in Sequential Logic Design ...
4.2. SR Flip-Flops SR flip-flops are the simplest form of single-bit memory (latch). A Latch is also known as a bi-stable memory ...
K-map for flip-flops K-maps can be generated based on flip-flops PS/NS table. The following K-map is for a SR flip-flop. Not ...
4.3. Asynchronous Sequential Logic Issues A circuit that uses latches (flip-flops) but does not use a clock to synchronize all s ...
Note that depending on if S changed first (case 1) or R changed the first (Case 2), final state will be different, which means w ...
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