VHDL Programming

242 Chapter Nine a2and one output pin o1. The cell requires 5 units of area, and the input pins have 1 unit of loading capacitan ...

Synthesis 243 In the preceding technology library, the intrinsic delays are given in the cell description. The loading delay is ...

244 Chapter Nine Created by User Translate Optimize Map to Gates VHDL RTL Description Unoptimized Boolean Description Optimized ...

Synthesis 245 and then try to reduce the logic generated by sharing common terms (in- troducing intermediate variables). Flatten ...

246 Chapter Nine there are a number of circuits that are difficult to flatten, because the number of terms created is extremely ...

Synthesis 247 the critical path was flattened for speed and the rest of the design was factored for small area and low fanout. A ...

Figure 9-9Smaller but Slower 8-Bit Ripple Carry Adder. 248 ...

249 Figure 9-10Bigger but Faster 8-Bit Lookahead Adder. ...

250 Chapter Nine In most synthesis tools, the designer has control over which type of adder is selected through the use of const ...

Chapter 10 VHDL Synthesis In this chapter, we focus on how to write VHDL that can be read by synthesis tools. We start out with ...

252 Chapter Ten c a d b out out in [1] in [0] in [1] in [0] Figure 10-1 Model Implementation. Simple Gate — Concurrent Assignmen ...

VHDL Synthesis 253 b c a PAD PAD PAD INBUF INBUF INBUF Y YYD Y A B C OUTBUF NANDOC PAD d Figure 10-2 3-Input OR. 3-input ORfunct ...

254 Chapter Ten c a d b out out in [1] in [0] in [1] in [0] Figure 10-3 Another 3-Input OR Implementation. IF ((smoke = ‘ 1 ’) A ...

VHDL Synthesis 255 back_door burg_alarm fire_alarm water_alarm side_door front_door smoke main_disable water_detect alarm_disabl ...

256 Chapter Ten Case Control Flow Statements The next example is an implementation of a comparator. There are two 8- bit inputs ...

VHDL Synthesis 257 gte <= ‘ 1 ’; END IF; WHEN less_equal => IF (a > b) THEN lte <= ‘ 1 ’; END IF; END CASE; END PROC ...

Figure 10-5 A Sample Synthesized Output. PORT( clock, din : IN std_logic; PORT( dout : OUT std_logic); END dff; ARCHITECTURE syn ...

VHDL Synthesis 259 The description contains a synthesizable entity and architecture rep- resenting a D flip-flop. The entity con ...

260 Chapter Ten PORT( clock, reset, din : IN std_logic; PORT( dout : OUT std_logic); END dff_asynch; ARCHITECTURE synth OF dff_a ...

VHDL Synthesis 261 Asynchronous Preset and Clear Is it possible to describe a flip-flop with an asynchronous presetand clear? As ...