VHDL Programming

322 Chapter Thirteen Process regprocis triggered when a rising edge occurs on input clk. When the process is triggered, input ai ...

CPU: Synthesis Description 323 architecture rtl of regarray is type t_ram is array (0 to 7) of bit16; signal temp_data : bit16; ...

324 Chapter Thirteen Shift The next device to be described is the shiftentity. The shiftentity is used to perform shifting and r ...

CPU: Synthesis Description 325 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 ••••••••• Shift Left '0' 0 0 0 0 ...

326 Chapter Thirteen 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 ••••••••• Rotate Left 0 0 0 0 0 0 0 0 0 0 0 ...

CPU: Synthesis Description 327 When a rising edge is applied to input clk, the data on input ais stored in the register. Input e ...

328 Chapter Thirteen q <= “XXXXXXXXXXXXXXXX” after 1 ns; -- exemplar_translate_on end if; end process; end rtl; The functiona ...

CPU: RTL Simulation In this chapter, a VHDL simulator is used to verify the functionality of the CPU VHDL RTL description. The V ...

330 Chapter Fourteen Top Level Stimulus Driver Design Under Test Figure 14-1 Top-Level Design Structure. Testbenches A testbench ...

CPU: RTL Simulation 331 Testbench Stimulus Driver DUT OK Errors Good Results Figure 14-2 Testbench Block Diagram. Kinds of Testb ...

332 Chapter Fourteen PACKAGE count_types IS SUBTYPE bit8 is INTEGER RANGE 0 to 255; END count_types; LIBRARY IEEE; USE IEEE.std_ ...

CPU: RTL Simulation 333 combinational process and a sequential process. The combinational process calculates the next state of t ...

334 Chapter Fourteen clk_en => clk_en, din => din, qout => qout); -- provide stimulus and check the result test: PROCES ...

CPU: RTL Simulation 335 -- read din value read(l, tmpdin, good_val); assert good_val REPORT “bad din value “; clk <= tmpclk; ...

336 Chapter Fourteen In the counter example, the first value read is the clksignal. The Tex- tIOstatement reads a STD_LOGICvalue ...

CPU: RTL Simulation 337 early in the design process when no known good results exist to verify against. When the results are ver ...

338 Chapter Fourteen up_dwn => up_dwn, clk_en => clk_en, din => din, qout => qout); -- provide stimulus and check th ...

CPU: RTL Simulation 339 read(l, space); --- skip a space -- read din value read(l, tmpdin, good_val); assert good_val REPORT “ba ...

340 Chapter Fourteen 20 0101 10 255 30 1001 0 10 40 0001 0 10 50 1001 0 8 60 0001 0 8 70 1001 0 7 80 0001 0 7 90 1001 0 6 100 01 ...

CPU: RTL Simulation 341 -- setup the clock force -repeat 20 clk 0 0, 1 10 -- log the results to a file list * -- setup initial s ...